Conventionally, in order to, for example, improve reliability, narrow a picture frame region, and reduce a manufacturing cost in the field of display devices, particularly, liquid crystal display devices, pixel TFTs provided in a display region of a liquid crystal display device are provided monolithically with driving TFTs provided in a scanning signal line driving circuit and a data signal line driving circuit that are provided in a peripheral region of the display region, by use of a semiconductor film, such as p-Si (polycrystalline silicon), CG-Si (continuous grain silicon) or microcrystalline silicon (μc-Si), which has a relatively high mobility.
Recently, in order to reduce the manufacturing cost, the pixel TFTs are provided monolithically with the driving TFTs provided in the scanning signal line driving circuit, by use of an a-Si (Amorphous Silicon) semiconductor film that can be formed at a lower cost without any crystallization process, though the a-Si semiconductor film has a mobility lower than that of the semiconductor film made from p-Si, CG-Si or microcrystalline silicon. In other words, monolithically forming a scanning signal line driving circuit by use of an a-Si semiconductor film (monolithically forming a gate driver) has been proposed.
The number of data signal lines is increased as a liquid crystal display device becomes high-resolution. Therefore, a data signal line driving circuit frequently includes data signal line driving circuits 116a, 116b and 116c (see FIG. 18).
FIG. 18 illustrates a configuration of a conventional liquid crystal display device 141 including the data signal line driving circuits 116a, 116b and 116c. 
The liquid crystal display device 141 includes a display panel 112, a flexible print substrate 113, and a control substrate 114.
In the display panel 112 of the liquid crystal display device 141, pixel TFTs 121 provided for respective pixels in a display region 112a, and driving TFTs provided in a scanning signal line driving circuit 115 are incorporated by use of amorphous silicon formed on a glass substrate.
A plurality of pixels PIX are arranged in a matrix manner in the display region 112a. A pixel PIX includes a pixel TFT 121, a liquid crystal capacitor CL, and a storage capacitor Cs.
The pixel TFT 121 has a gate electrode connected to a corresponding one of scanning signal lines GL, a source electrode connected to a corresponding one of data signal lines SL, and a drain electrode connected to the liquid crystal capacitor CL and the storage capacitor Cs.
The scanning signal lines GL are made up of scanning signal lines GL1, GL2, GL3, . . . , and GLn. The scanning signal lines GL are connected to respective output terminals of the scanning signal line driving circuit 115. The data signal lines SL are made up of data signal lines SL1, SL2, SL3, . . . , and SLm. The data signal lines SL each are connected to a corresponding output terminal of the data signal line driving circuit 116a, 116b or 116c. 
The storage capacitors Cs provided for the respective pixels PIX each have an electrode connected to a storage capacitor line (not shown) via which a storage capacitor voltage is applied to the electrode.
The scanning signal line driving circuit 115 is provided on a side of the display region 112a of the display panel 112, to which side the scanning signal lines GL1, GL2, GL3, . . . , and GLn extend (see FIG. 18). The scanning signal line driving circuit 115 sequentially supplies a scanning pulse (a gate pulse) to the scanning signal lines GL1, GL2, GL3, . . . , and GLn.
The scanning signal line driving circuit 115 can be provided monolithically with the display region 112a in the display panel 112 by use of a p-Si film, a CG-Si film, a microcrystalline silicon film, or an amorphous silicon film.
The data signal line driving circuits 116a, 116b and 116c are provided on the flexible print substrate 113, and supply data signals to the data signal lines SL1, SL2, SL3, . . . , and SLm.
The control substrate 114 is connected to the flexible print substrate 113, and supplies necessary signals and voltages to the scanning signal line driving circuit 115 and the data signal line driving circuits 116a, 116b and 116c. That is, the control substrate 114 supplies the necessary signals and voltages to the scanning signal line driving circuit 115 of the display panel 112 via the flexible print substrate 113.
In a case where the data signal line driving circuits 116a, 116b and 116c constitute a data signal line driving circuit as illustrated in the liquid crystal display device 141 of FIG. 18, a manufacturing cost and a mountable surface area will be increased.
In order to solve such a problem, there has been proposed a liquid crystal display device for carrying out an SSD (Source Shared Driving) method in which (i) the number of outputs from a data signal line driving circuit is decreased, and (ii) data signal lines provided for respective R, G and B are driven in a time division manner.
FIG. 19 exemplifies a liquid crystal display device 151 for performing an SSD method.
Note that a configuration of each of pixels PIX arranged in a matrix manner (see FIG. 19) is identical to that of the pixels PIX illustrated in FIG. 18, and therefore description of the configuration is omitted here.
The liquid crystal display device 151 includes a display panel 112, and a flexible print substrate 113. The display panel 112 includes the pixels PIX, a scanning signal line driving circuit (a gate driver) 153, and an SSD circuit 155. A data signal line driving circuit (a source driver) 152 having a chip shape is mounted on the flexible print substrate 113 (see FIG. 19).
A plurality of sets of three data signal lines are provided adjacent to each other in the display region 112, each of which sets includes a data signal line RSL connected to an R (red) pixel PIX, a data signal line GSL connected to a G (green) pixel PIX, and a data signal line BSL connected to a B (blue) pixel PIX.
FIG. 19 illustrates (i) the (n−1)-th set of data signal lines SLn−1 (RSLn−1, GSLn−1, and BSLn−1), (ii) the n-th set of data signal lines SLn (RSLn, GSLn, and BSLn), and (iii) (n+1)-th set of data signal lines SLn+1 (RSLn+1, GSLn+1, and BSLn+1).
The SSD circuit 155 includes (i) transistors (TFT) ASWR (ASWRn−1, ASWRn, and ASWRn+1 illustrated in FIG. 19) connected to edges of the respective data signal lines RSL, to each of which edges a data signal is to be supplied, (ii) transistors ASWG (ASWGn−1, ASWGn, and ASWGn+1 illustrated in FIG. 19) connected to edges of the respective data signal lines GSL, to each of which edges a data signal is to be supplied, and (iii) transistors ASWB (ASWBn−1, ASWBn, and ASWBn+1 illustrated in FIG. 19) connected to edges of the respective data signal lines BSL, to each of which edges a data signal is to be supplied.
For example, the transistors ASWRn, ASWGn, and ASWBn, having edges connected to the respective data signals lines RSLn, GSLn and BSLn belonging to an identical set, have respective other edges connected to one another. The other edges are connected to a corresponding output line DATA (DATAn illustrated in FIG. 19) of the data signal line driving circuit 152 (see FIG. 19).
In the liquid crystal display device 151 including such an SSD circuit 155, the number of output lines DATA in the data signal line driving circuit 152 can be reduced to one-third of the total number of output lines DATA in the data signal line driving circuits 116a, 116b and 116c provided in the liquid crystal display device 141 illustrated in FIG. 18, each of which data signal line driving circuits 116a, 116b and 116c is made up of chips. Further, the number of data signal line driving circuits provided in the liquid crystal display device 151 can be reduced to one-third of the number of the data signal line driving circuits provided in the liquid crystal display device 141. It is therefore possible to prevent increase in manufacturing cost and mountable surface area.
The following description will discuss in detail a configuration of the SSD circuit 155 with reference to FIG. 19.
The transistors ASWR, ASWG, and ASWB are sequentially turned on in a time division manner during substantially one-third of one horizontal period when respective ON signals Ron, Gon and Bon are inputted to gate electrodes of the respective transistors ASWR, ASWG, and ASWB. The transistor ASWR is turned on in response to an ON signal Ron of High level. This causes output DATA for a corresponding R pixel PIX to be supplied from the data signal line driving circuit 152 to a corresponding data signal line RSL. The transistor ASWG is turned on in response to an ON signal Gon of High level. This causes output DATA for a corresponding G pixel PIX to be supplied from the data signal line driving circuit 152 to a corresponding data signal line GSL. The transistor ASWB is turned on in response to an ON signal Bon of High level. This causes output DATA for a corresponding B pixel PIX to be supplied from the data signal line driving circuit 152 to a corresponding data signal line BSL.
That is, the transistors ASWR, ASWG, and ASWB have respective source electrodes and respective drain electrodes, ones of the source electrodes and the drain electrodes being connected to the respective data signal lines RSL, GSL, and BSL, and the other ones of the source electrodes and the drain electrodes being connected to a corresponding output line DATA of the data signal line driving circuit 152 (see FIG. 19).
The scanning signal line driving circuit 153 and the SSD circuit 155 can be incorporated in the display panel 112 monolithically with pixel TFTs 121 provided in a display region of the display panel 112, by use of a p-Si film, a CG-Si film, a microcrystalline silicon film, an oxide semiconductor film, or an amorphous silicon film.
Meanwhile, a TFT having a channel width wider than that of a conventional TFT should be employed in a case where driving TFTs do not meet a predetermined mobility required for circuit driving, particularly in a case where the driving TFTs are formed by use of an amorphous silicon film, which driving TFTs are provided in each of a scanning signal line driving circuit, a data signal line driving circuit and an SSD circuit that can be thus incorporated monolithically with pixel TFTs provided in a display region of a liquid crystal display device, by use of a p-Si film, a CG-Si film, a microcrystalline silicon film, an oxide semiconductor film, or an amorphous silicon film.
FIG. 20 is a view exemplifying a TFT having a wide channel width.
(a) of FIG. 20 is a view illustrating a part of a TFT, with a wide channel width, which includes a consecutive U-shape (comb teeth shape) electrode.
(a) of FIG. 20 illustrates a partial region 200 of a plurality of partial regions 200 included in the TFT. The partial region 200 includes a gate electrode line 210, a source electrode line 230, and a drain electrode line 240. The source electrode line 230 has an U-shape part surrounding an I-shape part of the drain electrode line 240. A channel is formed between the U-shape part and the I-shape part.
The TFT includes the plurality of partial regions 200 connected in juxtaposition with one another (not shown in (a) of FIG. 20).
The channel has (i) a width represented by a distance W of 2×DL1+DL2 and (ii) a length represented by a distance L between a first boundary and a second boundary (see (a) of FIG. 20). The first boundary is between the source electrode line 230 and a channel region. The second boundary is between the drain electrode line 240 and the channel region.
The TFT thus includes the plurality of partial regions 200 connected in juxtaposition with one another. It is therefore possible to provide a TFT having a remarkably wide channel width.
There is, however, a problem that an abnormality occurs in a property of the whole TFT configured as illustrated in (a) of FIG. 20 when even just a leak is generated between the source electrode line 230 and the drain electrode line 240.
Therefore, in a case where a short cut is caused between the U-shape part of the source electrode line 230 and the I-shape part of the drain electrode line 240 by, for example, a defect during a process, an upper part of the I-shape part of the drain electrode line 240 is melted and separated by use of laser, so that the whole TFT can normally operate.
In a case, however, where the I-shape part of the drain electrode line 240 is melted and separated by use of laser, the laser reaches a layer in which a semiconductor layer and an n+ layer are stacked, which layer is formed in an upper region of the gate electrode line 210. This is because a distance between a main body of the drain electrode line 240 and the upper region of the gate electrode line 210 is short in the TFT configured as illustrated in (a) of FIG. 20.
The layer, damaged by the laser, further transmits heat generated by the laser to a region adjacent to the layer because the layer extends to the whole TFT. This causes damage over a broad area including the region adjacent to the layer.